1. Field of the Invention
The present invention generally relates to increasing the yield of integrated circuit devices and more particularly to an improved methodology for forming redundant vias and increasing spacing between vias.
2. Description of the Related Art
Due to the nature of the CMOS manufacturing process, it is sometimes desirable to modify a ground-rule-correct VLSI design for the purpose of increasing reliability or manufacturing yield. One way to achieve this is to add redundancy to contacts or vias, and in certain circumstances, it is beneficial to increase the spacing between vias that are on the same level or are on different levels. The advantages of automating the insertion of redundant contacts or the separating of vias are self-evident; VLSI designs can contain millions of vias, and any attempt to do such layout modification by hand would be prohibitively expensive. In addition, by automating these activities, the results can be discarded and then easily regenerated if the layout changes or the manufacturing ground rules change.